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设计易测试的DSP软件

Design DSP Software for Testability
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作者 Jeremy Faller
出处 《电子产品世界》 2006年第11X期78-79,共2页 Electronic Engineering & Product World
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  • 1[1]M A Breuer. The Effect of Races, Delavs and Delay Fanlts on Test Generation[J]. IEEE Trans on Computers, 1974, 22(10): 1078 -1092.
  • 2[2]C J Lin, S M Redv.On Delay Fault Testing in Logic Circuits [J].IEEE Trans Computer-Aided Design, 1987, 6(5) :694 - 703.
  • 3[3]E S Park, M R Mercer, T W Williams. The Total Delay Fault Model and Statistical Delay Fault Coverage [J] . IEEE Trans on Computers, 1992, 41 (6) :688 - 698.
  • 4[4]K T Cheng, S Devadas, K Keutzer. Robust Delay-Fault Test Generation and Synthesis for Testability Under a Standard Scan Design Methodology[A] .Proc of 28th DAC[C]. 1991.80- 86.
  • 5[5]S Devadas, K Keutzer. Validatable Nonrobust Delay-Fault Testable Circuits via Logic Synthesis [J]. IEEE Trans on Computer-Aided Design, 1992,11 (12): 1559 - 1573.
  • 6[6]A Krstic,K T Cheng. Generation of Higb Quality Tests for Functional Sensitizable Paths [A].Proc of VLSI Test Symp [C].1995. 374 - 379.
  • 7[7]K T Cheng, H C Chen. Classification and Ideutification of Nonrobust Untestable Path Delay Faults[J]. IEEE Trans Computer-Aided Design of ICs and Systems, 1996, 15(8) :845 - 853.
  • 8[9]Z Li, Y Min, R K Brayton. Efficient Identification of Non-Robustly Untestable Path Delay Faults[ A]. Pric of Int'l Test Conf [C].1997. 992 - 997.
  • 9[10]U Sparmann, D Luxenburger, K T Cheng, et al.Fast Identification of Robust Dependent Path Delay Faults[A]. Proc of 32nd Design Automation Conf[C]. 1995.119- 125.
  • 10[11]M Sivaraman, A J Strojwas.A Unified Approach for Timing Verification and Delay Fault Testing[M]. Kluwer Academic Publishers,1998.

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