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Five modified boundary scan adaptive test generation algorithms 被引量:1

Five modified boundary scan adaptive test generation algorithms
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摘要 To study the diagnostic problem of Wire-OR (W-O) interconnect fault of PCB (Printed Circuit Board), five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Global-diagnosis sequence algorithm to replace the equal weight algorithm of primary test, and the test time is shortened without changing the fault diagnostic capability. The descriptions of five modified adaptive test algorithms are presented, and the capability comparison between the modified algorithm and the original algorithm is made to prove the validity of these algorithms. To study the diagnostic problem of Wire-OR (W-O) interconnect fault of PCB (Printed Circuit Board), five modified boundary scan adaptive algorithms for interconnect test are put forward. These algorithms apply Global-diagnosis sequence algorithm to replace the equal weight algorithm of primary test, and the test time is shortened without changing the fault diagnostic capability. The descriptions of five modified adaptive test algorithms are presented, and the capability comparison between the modified algorithm and the original algorithm is made to prove the validity of these algorithms.
出处 《Journal of Systems Engineering and Electronics》 SCIE EI CSCD 2006年第4期760-763,768,共5页 系统工程与电子技术(英文版)
关键词 boundary scan adaptive test interconnect test algorithm. boundary scan, adaptive test, interconnect test, algorithm.
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同被引文献7

  • 1Niu Chun-ping,Ren Zhe-ping,Chen Sheng-jian,et al.Adaptive in-terconnect diagnosis algorithm for W-A and W-O+W-A[].ISTM/.2007
  • 2Jarwala N,Yau C W.A new framework for analyzing test genera-tion and diagnosis algorithms for wiring interconnects[].Proc Int Test Conference.1989
  • 3Feng Wen-yi,Meyer F J,Lombardi F.Two-step algorithms for maxi-mal diagnosis of wiring interconnects[].Twenty-Ninth Annual In-ternational Symposium on Fault-Tolerant Computing.1999
  • 4P.Goel,M.T.McMahon.Electornic Chip In-place Test[].International Test Conference.1982
  • 5Yau C W,Najmi Jarwala.A unified theory for designing optimal test generation and diagnosis algori- thms for board interconnects[].Proc Int Test Confer- ence.1989
  • 6Lien Jung Cheun,Melvin A breuer.Maximal diagnosis for wiring networks[].Int Test Conference.1991
  • 7Wenyi Feng,Fred J Meyer,and Fabrizio Lombardi."Adaptive Algorithms for Maximal Diagnosis of Wiring Interconnects"[].IEEE Transactions on Computers.2003

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