AVS视频解码器的一种结构设计与硬件实现

Decoder architecture and hardware implementation for AVS-video

为了推动音视频编码标准(AVS)解码芯片产业的发展,提出了一种针对AVS视频标准基准档次4.0级别解码器的超大规模集成电路(VLSI)实现结构.通过分析实现复杂度,阐述了AVS视频解码器的总体框架、主要模块的功能及结构.解码器采用块级流水结构,主要模块之间实现并行处理.同时根据AVS算法特点,给出了变长解码模块、反整数余弦变换模块和环路滤波模块的硬件实现结构.解码器在现场可编程门阵列(FPGA)上实现,并给出了各模块的FPGA资源占用情况.实现结果表明,该AVS视频解码器实现结构能在54 MHz时钟频率下完成对25帧/s、720×576、4∶2∶0格式AVS码流的实时解码.

To promote the development of the audio video coding standard （AVS） chip industry, a very large scale integration （VLSI） implementation architecture for AVS-video Jizhun profile 4.0 level decoder was proposed. By analyzing the implementation complexity, the overview framework of the AVS video decoder, the function and architecture of the main modules were introduced. Block level pipelining architecture was adopted in the proposed decoder, and the parallel process between main modules was realized. Based on the characteristics of AVS algorithms, hardware architectures of variable length decoding module, inverse integer cosine transform module and in-loop deblocking filter module were developed. The decoder was implemented in the field programmable gate array （FPGA） and the resources consumed by different modules were obtained. The implementation results show that the architecture for AVS video decoder can satisfy real-time decoding of 25 frame/s, 720）〈576, 4 ： 2：0 AVS video at the clock frequency of 54 MHz.