二辅助通道雷达副瓣对消处理的FPGA实现

Two Assistant Antennas Radar Side-lobe Canceling Using FPGA

传统的副瓣对消处理多基于通用DSP。为了在由FPGA构建的板级信号处理器上实现雷达副瓣对消处理,可以将副瓣对消的算法采用一种专用硬件架构来实现。在开发电路时充分考虑设计的可移植性,为以后类似的任务提供IP。基于硬件乘法器复用的方法设计的电路,已经过FPGA验证,实测对消比大于20 dB,达到了预定指标,并已应用于工程实践。

Commonly,side- lobe canceling processing was based on general DSP before. There is a request to implement the radar side - lobe canceling on a board level signal processing system based on FPGA. A specific hardware architecture can be used to meet this request. During implementation）reuse of the circuit must be considered for subsequent project. This method based on reusable multiplier and the hardware architecture has been verified correct in a FPGA chip and hit the target. The ratio of canceling is greater than 20 dB. Now this design has been used in the engineering practice.