一种使用浮动电源线嵌入式超低功耗SRAM的设计

An Ultra-Low-Power Embedded SRAM with Floating Power Rails

为了解决存储单元的亚阈值泄漏电流问题,分析了在深亚微米下静态随机存储器(SRAM)6-T存储单元静态功耗产生的原因,提出了一种可以有效减小SRAM静态功耗浮动电源线的结构,并分析在此结构下最小与最优的单元数据保持电压;最后设计出SRAM的一款适用于此结构的高速低功耗灵敏放大器电路.仿真测试表明,使用浮动结构的SRAM的静态功耗较正常结构SRAM的静态功耗大大减小.

The paper analyses the standby power dissipation of standard SRAM 6-T cells. It also presents a new SRAM array structure with floating power rails and analyses the minimized and the optimal data retention voltage （DRV）. Besides, the paper presents a low-power sense amp｜ifier（SA）. The simulation results shows that the new structure saves a lager amount of energy than the traditional structure.