Logical Effort理论在电路设计中的应用

Implementation of Logical Effort in the Circuit Design

介绍了一种对于包含较长互连线的CMOS电路的优化方法,该方法是在Logical Effort理论基础上加入互联电阻模型得到的。这是一种简单的延迟模型,非常适合于快速而又有效的手工计算。有助于快速的预测电路的最小延迟,并以此优化电路的结构和逻辑门的尺寸。通过仿真证明了,当逻辑结构不是简单的反相器时,一样可以通过带互联电阻模型的Logical Effort模型得到简单的优化方案。

This paper presents a methodology for optimizing delay of circuits that consist of general CMOS logic gates and long interconnections. The methodology is based on an extension of the concept of logical effort. It is a simple delay model and good for insight and quick hand calculation. It helps you find the best number of stages,the best size of each gate, and the minimum delay of a circuit. Then this paper has demonstrated that it is possible to find simple solutions for delay optimization in the presence of resistive interconnections,even when all the gates are not simple inverters.