FPGA中通用互连结构的设计与优化

Design and Optimization for the General Interconnect Architecture of FPGA

介绍了一款基于SRAM技术的FPGA电路的通用互连结构。在对其通用互连线的延时模型进行分析的基础上,提出了一种改进的互连结构。基于CSMC 0.6μm工艺下的SPICE仿真及流片结果表明,改进后的互连结构性能提高了约10%。

The interconnect architecture of a new type of FPGA based on SRAM was designed. The general interconnect architecture was investigated through its delay model. A proved architecture was introduced. Simulation in SPICE based on the CSMC 0.6 μm CMOS process and experiments showed that the proved architecture was 10% better in speed.