期刊文献+

用二叉决策图学习加速测试模式生成

Speedup Generation Method for Test Pattern Based on BDD Learning
下载PDF
导出
摘要 提出了基于总会聚点的有序二叉决策图(BDD)学习方法,用以提高使用布尔可满足性方法的组合电路测试模式生成系统的性能.它有效地结合了基于布尔可满足性、BDD和结构等方法各自的优点,可以有效地解决局部信号赋值之间的关联性.其具体的做法是:首先分析电路的拓扑结构,收集局部信号的关联信息,构造局部电路结构的BDD图;之后从该图中学习出引起冲突赋值的合取范式子句,将这些学习的子句增补到子句库中,用以限制和修剪测试生成的搜索空间,从而加速测试模式的生成过程.实验结果说明了该方法的有效性. A TRL-based (total reconvergence line) BDD (binary decision diagram) learning heuristics is presented in this paper to improve the efficiency of test pattern generation for combinational circuits based on the Boolean satisfiability (SAT) method. This heuristics dovetail the respective strengths of BDD and SAT and circuit structure based methods to solve local signal correlations. More specifically, it first makes an analysis of the circuit topological structure to gather the information on local signal correlation by means of BDD learning. Then the above learned information in the conjunctive normal form clauses is used to restrict and focus the overall search space of SAT-based test pattern generation. The experimental results demonstrate the validity of this approach.
作者 刘歆 熊有伦
出处 《测试技术学报》 2007年第1期63-69,共7页 Journal of Test and Measurement Technology
基金 国家自然科学基金资助项目(50390060 50335020)
关键词 测试模式生成 布尔可满足性 二叉决策图学习 test pattern generation boolean satisfiability binary decision diagram learning
  • 相关文献

参考文献16

  • 1Kwang T C, Krstic A. Current Directions in Automatic Test Pattern Generation[J]. IEEE Computer, 1999, 32(1): 58-64.
  • 2Hamzaoglu I, Patel J H. New Techniques for Deterministic Test Pattern Generation[C]. Proceedings of the 16th IEEE VLSI Test Symposium, 28 April - 1 May 1998, Princeton, NJ, USA:IEEE Computer Society, 1998: 446-452.
  • 3Wang C, Sudhakar M, Reddy S M, et al. Conflict Driven Techniques for Improving Deterministic Test Pattern Generation[C]. Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design, San Jose,California, USA, November 10-14, 2002. New York, NY, USA: ACM Press, 2002: 87-93.
  • 4Larrabee T. Test Pattern Generation Using Boolean Satisfiability[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992, 11(1): 4-15.
  • 5Stephan P, Brayton R K, Sangiovanni-Vineentelli A L. Combinational Test Generation Using Satisfiability[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996, 15 (9): 1167-1176.
  • 6Tafertshofer P, Ganz A, Antreich K. IGRAIN-An Implication Graph-Based Engine for Fast Justification and Propagation in the Implication Graph[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000, 19(8): 907-927.
  • 7Gizdarski E, Fujiwara H. SPIRIT: A Highly Robust Combinational Test Generation Algorithm[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002, 21 (12): 1446-1458.
  • 8Zhang L, Madigan C F, Moskewicz M H. Efficient Conflict Driven Learning in a Boolean Satisfiability Solver[C].Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, USA,November 4-8, 2001. New York, NY, USA: ACM Press, 2001: 279-285.
  • 9Silva L G, Silveira L M, Marques-Silva J. Algorithms for solving Boolean satisfiability in combinational circuits[C].Proceedings of Design Automation and Test in Europe (DATE), 9-12 March 1999, Munich, Germany. IEEE Computer Society, 1999, 526-530.
  • 10Brglez F, Fujiwara H. A Neutral Netlist of 10 Combinatorial Benchmark Circuits and a Target Translator in Fortran[C]. Special Session on ATPG and Fault Simulation, Proceedings of IEEE International Symposium on Circuits and Systems. Kyoto: IEEE, 1985: 663-698.

共引文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部