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基于时间随机化的密码芯片防攻击方法 被引量:8

Modeling Timing Randomization in Cryptographic Chip Against Power Analysis Attack
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摘要 差分功耗分析(DPA)作为一种获取密码芯片密钥的旁道攻击方法,对目前的信息安全系统构成了严峻挑战。作为防御技术之一,将系统运行时间随机化是一种直接有效的方法。该文建立了随机时间延迟防御DPA攻击的理论模型,从而得到了随机时间延迟抑制DPA攻击的阈值条件。为了既保证较高的DPA防御能力,又能降低计算设备额外的时间负担,基于理论模型的结论研究了时间延迟的概率分布,得出了发生一次和两次随机时间延迟时,延迟变量最优的概率分布律。 Differential power analysis attack (DPA) is a powerful tool for retrieving secrets embedded in cryptographic devices and it has been a considerable threat to the information security system. As an attractive countermeasure, inserting random time delay into device's running process is a straightforward and effective method. This paper presents the theoretical modeling on timing randomization against power analysis attacks, and gives the threshold condition to resist DPA. In order to obtain the minimal amount of overhead, it investigates different probability distributions of random delay. The optimized probability distributions are proposed, when random delays are inserted one or two times.
出处 《计算机工程》 CAS CSCD 北大核心 2007年第2期6-8,共3页 Computer Engineering
基金 国家自然科学基金资助项目(90407002 60576024) 上海市科委AM基金资助项目(0502)
关键词 差分功耗分析攻击 密码芯片防御技术 时间随机化 概率分布 Differential power analysis(DPA) Countermeasure for cryptographic chip Timing randomization Probability distribution
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参考文献5

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同被引文献63

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  • 2韩军,曾晓洋,汤庭鳌.RSA密码算法的功耗轨迹分析及其防御措施[J].计算机学报,2006,29(4):590-596. 被引量:19
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  • 7Chari S, Rao J R, Rohatgi P. Template attacks//Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES' 03). Cologne, Germany, 2003 13-28
  • 8Agrawal D, Rao J R, Rohatgi P, Schramm K. Templates as master keys//Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES' 05). Edinburgh, UK, 2005: 15-29
  • 9Archambeau C, Peeters E, Standaert F X, Quisquater J J. Template attacks in principal subspaces//Proeeedings of the Workshop on Cryptographie Hardware and Embedded Systems (CHES'06). Yokohama, Japan, 2006, 1-14
  • 10Gierlichs B, Lemke-Rust K, Paar C. Templates vs. Stochastic Methods//Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES'06). Yokohama, Japan, 2006: 15-29

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