OpenCMP:一个支持事务存储模型的多核处理器模拟器

OpenCMP:A Simulator for CMP with Transactional Memory Model

CPU设计正在由仅开发指令级并行性的单线程单核结构转向利用线程级并行性的多线程多核结构,但至今还没有一个可移植性好并被广泛使用的开源多核处理器模拟器,限制了在这样的结构上开展高质量的研究工作。我们开发了一个多核处理器体系结构模拟器OpenCMP,用于支持当前和未来对多线程多核处理器体系结构关键技术的研究。该模拟器适当地抽象了多核处理器结构,为主流的多核处理器结构研究提供一个可扩展、灵活的模拟工具框架,包括支持对乱序、顺序的处理器核和同时多线程处理器核的模拟,以便对更大的多核设计空间进行比较性研究。本文以支持事务存储模型的多核处理器结构模拟器为例,详细描述了如何通过抽象多核结构和事务存储模型的最基本特性和组成部分,扩展单核处理器模拟器SimpleScalar,设计与实现一个多核处理器模拟器。初步研究表明,与现有的多核处理器模拟器相比,该模拟器能够较好地支持对事务存储模型和基于事务存储模型的多核处理器体系结构的研究。

For CPU design, a shift of focus from exploiting instruction-level parallelism with single-thread and singlecore to exploiting thread-level parallelism with techniques like Chip Multi-Proeessing（CMP） and Multi-Threading（MT） have been witnessed. Up to now, the lack of portable and widely disseminated simulators for CMP systems has doubt less contributed to a lower quantity of research occurring in those areas. We develope a CMP processor architectures simulator called OpenCMP as evaluation infrastructure to support current and future investigations on CMP arehiteeture. The tools set provides a scalable and flexible simulating framework for mainstream CMP machines, in which each core is flexible to simulate but-of-order cores and simple in-order cores, and have Simultaneous MultiThreading（SMT） support as well. This Will allow comparative studies. This paper describes the design of OpenCMP with transactional memory model, shows how to abstract the key characteristics and components of CMP and transactional memory model, and how to build the simulator based on the SimpleSalar Tool Set. Compared with other existing CMP simulators, OpenCMP has the flexible software model and allows the configuration of a large set of architectural parameters to evaluate the CMP architecture with transactional memory model.