摘要
采用深能级瞬态谱仪(DLTS)测试多晶硅n+p二极管势垒区深能级谱。利用DLTS实验结果,对G.Baccarina等提出的均匀陷阱模型进行修正,提出多晶硅晶粒间界的线性陷阱模型。运用该修正模型,可采用迭代法求得多晶硅电学参数──势垒高度Eb、电导率激活能Ea与多晶硅掺杂浓度Nc间关系。计算结果表明,多晶硅晶粒间界的线性陷阱模型具有理论合理性。
In this paper, the deep level transient spectrums of polysilicon n+pdiode depletion region have been measured by use of DLTS instrument. According to the DLTS experimental results, the uniform trapping model set by G. Baccarinaetc. has been modified and the linear trapping moael of the grain-boundary has been proposed. Using the modified model, the relationship between the polysilicon electrical parameters, barrier height Eb as well as activation energy Ea, and the dopping level NG can be solved iteratively. The calculation results show that the linear trapping model of the grain-boundary is possessed of theoretical reasonableness.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
1996年第4期336-343,共8页
Research & Progress of SSE
关键词
深能级瞬态谱
线性陷阱模型
晶粒间界
多晶硅
Deep Level Transient Spectroscopy Linear Trapping ModelGrain-Boundary Barrier Height Activation Energy