摘要
提出一种基于FPGA布通率的装箱算法.选择连接因子最小的节点作为种子节点;采用基于布通率的启发式函数来选择最合适的逻辑单元(LE)装箱到可配置逻辑单元(CLB)内部.可以同时减少装箱后CLB之间的线网数和CLB引脚的外部使用率,从而减少布线所需的通道数.该算法和已有算法相比较,线网数和布线通道数都减少约30%.算法的时间复杂度仍然是线性的.
In this paper, a packing algorithm based on routability is proposed. This method begins with selecting logic element (LE) with minimum connectivity factor as the seed of the packing, and then uses a heuristic function based on routability-driven to obtain the most appropriate LE to pack into the configurable logic block (CLB). The number of the used pins of the CLB and the inter-CLB wires can be reduced simultaneously. Both number of nets and routing tracks have been improved about 30 % when compared with previous algorithms. The time complexity of this algorithm is still linear.
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2007年第1期108-113,共6页
Journal of Computer-Aided Design & Computer Graphics
基金
上海应用材料科技合作共同计划项目(AM0406)
复旦大学青年科学基金(JKH1203001).