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基于布通率的FPGA装箱算法 被引量：5

A Routability Driven Packing Algorithm for FPGA
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摘要 提出一种基于FPGA布通率的装箱算法.选择连接因子最小的节点作为种子节点;采用基于布通率的启发式函数来选择最合适的逻辑单元(LE)装箱到可配置逻辑单元(CLB)内部.可以同时减少装箱后CLB之间的线网数和CLB引脚的外部使用率,从而减少布线所需的通道数.该算法和已有算法相比较,线网数和布线通道数都减少约30%.算法的时间复杂度仍然是线性的. In this paper, a packing algorithm based on routability is proposed. This method begins with selecting logic element （LE） with minimum connectivity factor as the seed of the packing, and then uses a heuristic function based on routability-driven to obtain the most appropriate LE to pack into the configurable logic block （CLB）. The number of the used pins of the CLB and the inter-CLB wires can be reduced simultaneously. Both number of nets and routing tracks have been improved about 30 % when compared with previous algorithms. The time complexity of this algorithm is still linear.
作者 胡云 王伶俐 唐璞山 童家榕
机构地区 复旦大学专用集成电路与系统国家重点实验室
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2007年第1期108-113,共6页 Journal of Computer-Aided Design & Computer Graphics
基金 上海应用材料科技合作共同计划项目(AM0406) 复旦大学青年科学基金(JKH1203001).
关键词 现场可编程逻辑门阵列 布通率 装箱 FPGA routability driven packing
分类号 TP391 [自动化与计算机技术—计算机应用技术]
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参考文献8

  • 1Marquardt A,Betz V,Rose J.Using cluster based logic blocks and timing-driven packing to improve FPGA speed and density[C] //Proceedings of ACM/ SIGDA International Symposium on FPGAs.New York:ACM Press,1999:37-46
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同被引文献44

  • 1徐新民,王倩,严晓浪.FPGA布线通道分布对面积效率的影响研究[J].电子与信息学报,2006,28(10):1959-1962. 被引量：2
  • 2倪刚,来金梅,童家榕.一种基于图模式匹配的逻辑单元映射算法[J].计算机辅助设计与图形学学报,2006,18(12):1850-1854. 被引量：4
  • 3Pandit A,Easwaran L,Akoglu A.Concurrent timing based and routability driven depopulation technique for FPGA packing[C]//Proceedings of International Conference on Electrical and Computer Engineering Technology.Piscataway:IEEE Computer Society Press,2008:325-328.
  • 4Betz V,Rose J.VPR:a new packing,placement and routing tool for FPGA research[C]//Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications.London:Springer,1997:213-222.
  • 5Eguro K,Hauck S.Simultaneous retiming and placement for pipelined netlists[C]//Proceedings of the 16th International Symposium on Filed-Programmable Custom Computing Machines.Los Alamitos:IEEE Computer Society Press,2008:139-148.
  • 6Eguro K,Hauck S.Enhancing timing-driven FPGA placement for pipelined netlists[C]//Proceedings of the 45th Annual Design Automation Conference.New York:ACM Press,2008:34-37.
  • 7Li S,Ebeling C.QuickRoute:a fast routing algorithm for pipelined architectures[C]//Proceedings of IEEE International Conference on Field-Programmable Technology.Los Alamitos:IEEE Computer Society Press,2004:73-80.
  • 8Eguro K,Hauck S.Armada:timing-driven pipeline-aware routing for FPGAs[C]//Proceedings of the 14th International Symposium on Filed Programmable Gate Arrays.New York:ACM Press,2006:169-178.
  • 9Gayasen A, Narayanan V, Kandemir M, et al. Designing a 3-D FPGA: switch box architecture and thermal issues [J]. IEEE Transactions on Very Large Scale Integration Systems, 2008, 16(7).. 882-893.
  • 10Anderson J H, Najm F N. Low-power programmable FPGA routing cireuitry [J]. IEEE Transactions on Very Large Scale Integration Systems, 2009, 17(8) ; 1048-1060.

引证文献5

二级引证文献4

计算机辅助设计与图形学学报
2007年 第1期

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