基于FPGA的数字音频渐进延迟器设计与算法分析

Design and Algorithm Analysis of the Digital Audio Gradual Delayer Based on FPGA

提出了一种基于FPGA的数字音频延迟器设计方案,通过线性内插和抽取算法实现数字音频信号的渐进延迟与直通,计算机仿真和实际应用验证了其正确性和可行性。该延迟器提供AES/EBU专业数字音频接口,可应用于全数字音频广播系统,以满足直播类节目对声音信号的延迟要求。

In this paper, a designing scheme of the digital audio gradual delayer based on FPGA is proposed. The gradual delay and catch of digital audio signal can be realized by the algorithm of the linear interpolation and extraction. The computer simulation and application show that the design is correct and feasible. The delayer provides the digital interface of AES/EBU, and could be applied in the digital audio broadcasting system to meet the demand of audio signal＇s delay in the live broadcasting program.