一种基于0.25μm CMOS工艺的锁相环电路设计

A PLL Design Based on 0.25um CMOS Process

锁相环在很多领域都得到了广泛应用。本文给出了一款全芯片集成锁相环电路设计,其工作输出频率范围在50M到150M之间,抖动在150ps以内,工作电压为2.5伏,该芯片采用了0.25μmCMOS工艺。本文主要阐述全芯片集成锁相环的设计方法,以及对各个参数的折衷设计考虑,最后给出了一些仿真结果和电路物理版图。

Phase-locked loop （PLL） has been applied in many fields. The paper shows the design about the full-chip integrated PLL with 0.25um CMOS process. The output frequency ranges from 50MHz to 150MHz, the jitter is less than 150ps, the power supply is 2.5v. The paper mainly gives the design method for the PLL, and shows some concerns about parameter tradeoffs. Finally, the paper shows the simulation results and layout.