基于FPGA的神经网络硬件实现方法

Neural networks hardware implementation based on FPGA

提出了一种可以灵活适应不同的工程应用中神经网络在规模、拓扑结构、传递函数和学习算法上的变化,并能及时根据市场需求快速建立原型的神经网络硬件可重构实现方法.对神经网络的可重构特征进行了分析,提出了三种主要的可重构单元;研究了可重构的脉动体系结构及BP网络到该结构映射算法;探讨了具体实现的相关问题.结果表明,这种方法不仅灵活性强,其实现的硬件也有较高的性价比,使用一片FPGA中的22个乘法器工作于100MHz时,学习速度可达432MCUPS.

For different engineering applications, neural networks varied in scale, topology, transfer functions and learning algorithms. A reconfigurable approach for neural hardware implementation was proposed, which was not only flexible to meet those changes, also with the fast prototyping ability for market requirements. Three kinds of reconfigurable processing units were presented based on the analysis of neural network＇s reeonfiguration. A reconfigurable systolic architecture was put forward and the method of mapping BP networks into this architecture was introduced. Implementation issues were discussed with an example. The results showed that a high learning speed of 432 M CUPS（Connections Updated Per Second）was achieved （working at 100 MHz using 22 multipliers） at a reasonable cost.