具有并发结构的CMOS数字乘法器设计

The Design of CMOS Digital Multiplier with Concurrent Structure

本文简要介绍了几种结构的数字乘法器。着重讨论了以大规模集成电路为基础的并发结构数字乘法器的设计和性能。给出了并发结构四位数字乘法器的功能模拟结果及CMOS工艺版图。

This paper presents briefly the digital multiplier with different structure. The design and performance of multiplier with concurrent structure based on large scale integrated circuits technique are discussed in detail. The functional simulation results and CMOS layout of concurrent multiplier are given.