期刊文献+

运用赋值相异生成高效率测试图形

Using Assignment Inconsistence to Generate High Efficient Test Patterns
下载PDF
导出
摘要 针对传统算法中赋值相异导致测试生成失败的问题,提出新的解决思路,利用赋值相异信息确认故障效应传播路径,以确保每次测试生成成功.与传统方法不同的是,新方法通过对故障传播函数的分析,总结出支配故障传播的规律,即故障传播不仅仅受线确认条件约束,还受敏化路径的拓扑结构的约束,线确认和蕴涵所导致的赋值相异有助于建立敏化正确的故障传播路径.进而提出自湮没和它湮没的概念和分析方法,并发展为运用赋值相异信息来确认故障效应传播路径的方法.新方法可生成精简的、故障覆盖率高的测试图形,并尽可能多地检测多重故障.基于ISCAS85Benchmark的实验结果表明,新方法的测试数据长度和故障覆盖率均优于Synopsys Tetramax等现有方法. To solve the problem that assignment inconsistence leads to failure of test generation in traditional algorithms, a novel method is developed to identify the correct paths for propagating fault effects by assignment inconsistence and ensure that every test generation is successful. In the method, the rules that dominate the fault propagation are summarized through analyzing fault propagation functions, namely, the faults propagation not only is constrained by line justification, but also depends on the topologies of the sensitized paths, It is found that the assignment inconsistence caused by the line justification and implication is helpful for creating sensitized paths. Moreover, the concept and analyzing method of self-masking and other-masking are presented. The proposed method can generate simplified test patterns with high fault coverage, and can detect multiple faults as many as possible. Experimental results based on ISCAS85 bench- mark show that the length of test data and coverage of the proposed method are superior to those of existing methods available.
作者 雷绍充 梁峰
出处 《西安交通大学学报》 EI CAS CSCD 北大核心 2007年第2期195-199,共5页 Journal of Xi'an Jiaotong University
关键词 赋值相异 测试生成 敏化路径 湮没 assignment inconsistence test generation sensitized path masking
  • 相关文献

参考文献11

  • 1Lingappan L,Ravi S,Jha N K.Satisfiability-based test generation for nonseparable RTL controller-datapath circuits[J].IEEE Trans on CAD,2006,25(3):544-557.
  • 2Mourad S.Principle of testing electronic systems[M].New York:John Wiley & Sons,Inc.,2000.
  • 3Bushnell L M,Vishwani D A.Essentials of electronic testing for digital,memory and mixed-signal VLSI circuits[M].Dordrecht,Netherlands:Kluwer Academic Publishers,2000.
  • 4Amyeen M E,Fuchs W K,Pomeranz I,et al.Fault equivalence identification in combinational circuits using implication and evaluation techniques[J].IEEE Trans on CAD,2003,22(7):922-936.
  • 5Dwarakanath K N,Blanton R D.Exploiting dominance and equivalence using fault tuples[C]∥Proc 20th IEEE VLSI Test Symposium.Los Alamitos,USA:IEEE CS Press,2002:269-274.
  • 6Stephan P,Brayton R,Sangiovanni A.Combinational test generation using satisfiability[J].IEEE Trans on CAD,1996,15(8):1167-1176.
  • 7Junhao S,Grschwin F,Drechsler R,et al.PASSAT:efficient SAT-based test pattern generation for industrial circuits[C]∥Proc IEEE Computer Society Annual Symposium on VLSI.Los Alamitos,USA:IEEE CS Press,2005:212-217.
  • 8Yang K,Cheng K T,Wang L C.TranGen:a SAT-based ATPG for path-oriented transition faults[C]∥IEEE Proc ASP-DAC 2004.Los Alamitos,USA:IEEE CS Press,2004:92-97.
  • 9Kameshwar C,Michael S H.Decision selection and learning for an 'all-solutions ATPG engine[C]∥Proceedings of International Test Conference.Los Alamitos,USA:IEEE CS Press,2004:607-616.
  • 10Lintao Z,Madigan C F,Moskewicz M H,et al.Efficient conflict driven learning in a Boolean satisfiability solver[C]∥IEEE/ACM International Conference on Computer Aided Design.Los Alamitos,USA:IEEE CS Press,2001:279-285.

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部