基于Cyclone系列FPGA的1024点FFT算法的实现

Implementation of 1024-point FFT Algorithm Based on Cyclone FPGA

介绍了一种用低成本Cyclone系列FPGA(现场可编程门阵列)实现基于按D IF(频率抽取)rad ix 2结构1 024点FFT(快速傅里叶变换)算法的方法。本设计采用Verilog语言编程实现,利用EDA(电子设计自动化)工具对设计进行了仿真、综合,并在开发板上实现板级验证,最后分析了整个设计的性能,说明在低成本Cyclone系列上可以实现高速FFT算法。

This paper describes an implementation of 1024-point FFT algorithm using Decimation in Frequency （DIF） radix 2 structure based on the low-cost FPGA of Altera（ Cyclone serials）. The system designed by Verilog HDL is simulated, synthesized by EDA tools and verified with the development board. At last, the performance of the whole system is analyzed. Experimental results show that the high speed of FFT can be realized by low-cost FPGA.