摘要
IP报文封装为链路帧是路由器设计必不可少的技术。提出了一种通用的多通道报文封装和转发的处理器结构,利用FP-GA内部存储资源,采用流水线和多队列缓存区相结合,显著提高了小报文线速转发和突发流量传输的性能。
IP packets encapsulation as link layer frames is necessary to a router design.In this paper,we present an universal processor architecture for multi-channel packets encapsulation and forwarding,combined with FPGA embedded memory blocks, pipeline and multi-queue buffer mechanism,which improvs the capability of short packets forwarding at wire-speed or burst flow transfer.
出处
《计算机工程与应用》
CSCD
北大核心
2007年第4期150-152,163,共4页
Computer Engineering and Applications
关键词
流水线
多队列
报文转发
pipeline
multi-queue
packets forwarding
