合成工艺对ZnVSb基压敏陶瓷性能的影响

Effect of fabrication processes on the properties of ZnVSb based varistor ceramics

研究了三种合成工艺对ZnVSb系压敏电阻烧结、显微结构和性能的影响。通过对陶瓷密度、显微结构及电学特性的检测、分析发现:化学计量比相同情况下,与V2O5+Sb2O3预热处理工艺相比,以SbVO4取代Sb2O3合成工艺及传统氧化物合成工艺逐步加剧了尖晶石相在材料中的形成和掺杂元素在晶界的偏聚;导致材料内部晶界势垒逐渐升高,材料的非线性系数及压敏电压逐渐上升。研究结果为ZVSb系压敏电阻材料的设计、制备提供了新的思路。

The sintering characteristics, microstructure and properties of ZnVSb based varistor ceramics were studied for three fabrication processes. Based on the examinations on the density, microstructure and electrical characteristics of the ceramics synthesized by the process involving a pre - heat - treatment of V2O5/Sb2O3 mixture of specific ratio, the process of substituting SbVO4 for Sb2O3 before fabrication and by the traditional oxide ceramic synthesizing process, a gradual increase of spinel formation within the ceramics, and the segregations of dopant element within the vicinity of ZnO grain boundaries were observed. These micro structural - changes within the ceramics contribute to the formation of higher grain boundary barrier which naturally leads to increasing the nonlinearity and break down voltage of the ceramics. The result of this study unveils a new way of tailoring the properties of ZnVSb based varistor ceramics according to application requirements.