基于锁相环的时间同步机制与算法

A Time Synchronization Mechanism and Algorithm Based on Phase Lock Loop

在讨论计算机时钟分析模型的基础上,分析和总结已有的时间同步机制的特点,提出了一种低能耗单向广播校正同步机制,同时进行时钟偏移补偿和漂移补偿,并基于传统的锁相环(phase locked loop,简称PLL)原理设计了同步算法.为了避免实现过程中额外的硬件开销,开发了一种简洁的数字锁相环.最后,在Mica2实验平台上对所设计的同步机制与算法进行了验证,并与已有的典型算法进行了性能比较.

In this paper, the analysis model of computer clock is discussed, and the characteristic of the existing synchronization mechanisms is summarized. Subsequently, a unidirectional reference broadcast synchronization mechanism with low power is developed, and this mechanism can achieve simultaneously the offset compensation and drift compensation. Its implementation algorithm is designed based on the principle of traditional phase locked loop （PLL）. In order to avoid introducing the extra hardware, a simple digital PLL is constructed. Finally, the validation is done on the Mica2 experimental platform, and the performance is evaluated and compared with the typical algorithms.