基于流水线的运动估计算法FPGA设计

Design of Motion Estimation Algorithm Based on Pipeline FPGA

块匹配算法(BMA)在目前运动估计算法中占主导地位,多级顺序排出算法(MSEA)是一种耗尽型,并具有精度特性的块匹配运动估计搜索算法,但是单靠软件的方法实现其运算速度并不能完全满足实时性要求。力求通过FPGA设计思想,达到实时处理的目的,首先对算法进行基本的FPGA硬件设计,然后将流水线结构应用到算法当中。实验结果表明,基本的硬件设计其运算速度相比于优化的软件方法提高了14倍以上。当引入流水线结构后,算法速度得到了进一步提高,从而为实时监控运动目标提供了可能。

Block matching algorithm is playing an important role in motion estimation at present. Multi -level successive elimination algorithm（ MSEA） is an exhausted block matching motion estimation search algorithm, which has a precision character. But its operation speed can not meet the requirement of real time application only by software method. The paper tries to achieve the real time using FPGA design. Firstly, it has been designed with basic FPGA hardware, and then the pipeline structure is applied to the algorithm. The speed of basic hardware method is over 14 times than that of the optimized software method. The speed is higher when the pipeline structure has been introduced into the basic hardware method. So the real time monitoring of moving target becomes possible.