AES密码算法的结构优化与实现

Architecture Optimization and Implementation of AES Algorithm

对AES密码算法的结构进行了优化,并应用0.6μmCMOS工艺实现了AES加密/解密芯片。使用Ver-ilogHDL进行算法建模,采用自动综合技术完成版图设计。芯片支持加密/解密模式及所有3种密钥长度。已完成流片,测试的最高时钟频率为20MHz,128位、192位和256位密钥时的数据吞吐率分别可达49.2Mbps、41.3Mbps和35.6Mbps。

This paper presents an architecture optimization for AES （Advanced Encryption Standard） algorithm, and a chip implementation using 0.61μm CMOS technology. Verilog HDL was used as the design entry, and the layout was designed by auto-synthesis tools. The designed chip supplies both the encryption and decryption modes and all the three kinds of AES key length. The observed data throughput rate was 49.2 Mbps for 128-bit keys, 41.3Mbps for 192-bit keys, and 35.6 Mbpa for 256-bit keys with a 20MHz clock.