可扩展公钥密码协处理器的设计与实现

Scalable VLSI Design and Implementation for Asymmetric Keys Cryptosystems Coprocessor

在信息安全领域中,公钥密码算法具有广泛的应用.模乘、模加(减)为公钥密码算法的关键操作,出于性能上的考虑,往往以协处理器的方式来实现这些操作.针对公钥密码算法的运算特点,本文提出了一种可扩展公钥密码协处理器体系结构以及软硬件协同流水工作方式,并且改进了模加(减)操作的实现方法,可以有效支持公钥密码算法.同时,该协处理器体系结构也可根据不同的硬件复杂度及性能设计折衷要求,进行灵活扩展.

In the application of information security,public key cryptographic algorithms play a very important role. The key operations of public key cryptosystems are modular multiplication,modular addition and subtraction,which are always implemented on specific arithmetic coprocessors for performance enhancement. Based on the requirement analysis of public key cryptographic algorithm acceleration,a scalable architecture of public key cryptography coprocessor is presented in this paper. An efficient method called software hardware co-pipeline is employed. Besides ,an efficient method for modular addition is introduced. The introduced hardware is capable of performing all the key operations of public key cryptography. At the same time ,this scal- able architecture provides an easy tradeoff between hardware circuit complexity and performance.