组相联Cache中漏流功耗优化技术研究

Leakage Power Optimization in Set-associative Caches

随着集成电路制造工艺进入超深亚微米阶段,漏电流功耗在微处理器总功耗中所占的比例越来越大,在开发新的低漏流工艺和电路技术之外,如何在体系结构级控制和优化漏流功耗成为业界研究的热点.Cache在微处理器中面积最大,是进行漏流控制和优化的首要部件.本文提出了一种LRU-assist算法,利用既有的LRU信息,在保证处理器性能不受影响的前提下,cache的平均关闭率可达53%,大大降低了漏电流功耗.

The leakage power issue is challenging high-performance microprocessor design, especially as feature size shrinks. Caches represent a sizable fraction of the total power consumption. Chipmakers have proposed many low leak design techniques, in which gated-vdd and cache decay are the most efficient circuit and architectural methods. Cache decay are based on counter overflow, and lose many low leak opportunities. In this paper, we use existing LRU information to aggressively clamp cache blocks, complementing the counter-based mechanism （we call it LRU-assist algorithm）. Simulation results show that, with little hardware cost and negligible performance loss （〈0. 1 % ）, LRU-assist decay can shut off 53% cache lines on average and greatly decrease the leakage power dissipation.