采用EPAL结构的绝热触发器及时序电路的研究

Study of low power flip-flops and sequential circuits using EPAL structure

在分析了EPAL电路的基础上，提出了基于EPAL电路的D触发器和JK触发器电路覆其基于这两种触发器的时序电路。用1．2mm的CMOS工艺参数对所设计的电路进行PSPICE模拟，模拟证明EPAL触发器和时序电路均能够完成正确的逻辑功能。模拟还证明，无论EPAL结构的D触发器电路和JK触发器，还是基于EPAL结构D触发器的具有自启动功能的4-bit环形计数器都比相应传统的静态CMOS电路有较大的能耗节省。因此EPAL结构的触发器电路和基于这两种触发器的时序电路比传统的CMOS触发器和时序电路有明显更低的功耗。

Based on the analysis of EPAL circuit, the D flip-flop and jK flip-flop and sequential circuits bused on EPAL flip-flop are proposed in this paper. The circuits proposed in this paper arc simulated by PSPICE at different clock frequencies using 1.2mm CMOS technology, Simulations prove that functions of proposed flip-flops and sequential circuits are correct. Simulations also prove that power savings of the circuits based on EPAL structure designed in this paper are evident, compared with their conventional CMOS opposites. So power dissipation of EPAL flip-flops and sequential circuits is obviously lower than that of conventional CMOS circuits.