一种基于FPGA的高效FIR滤波器的设计与实现

Design and Implementation of Efficient FIR Filter Based on FPGA

该文在介绍有限冲激响应(FIR)数字滤波器理论及常见实现方法的基础上,提出了一种基于FPGA的高效实现方案。该方案采用对称结构、加法和移位代替乘法运算、优化的CSD编码、流水线和级联技术等方面对传统的设计方法进行了改进,并借助FPGA滤波器芯片和Qu-artusⅡ软件、Matlab软件对该方案进行了仿真验证。仿真实验结果表明:此种FIR滤波器的实现方法运算速度快、实时性好、节省硬件资源,其性能优于传统的FIR滤波器设计方法。

This paper introduces the theories and common implementation methods of FIR （ Finite impulse response） digital filter. An efficient implementation design based on FPGA is presented. Symmetrical structure, special multiplication operation, canonic signed digit encoding, cascade technology and pipelining technology are used to improve the conventional design methods. The design is simulated with the FPGA chip, Quartus Ⅱ and Matlab software. The simulation result shows that this technique has such advantages as fast operation speed and economizing of devices. Its performance is much better than the conventional methods＇.