基于并行流水线结构的可重配FIR滤波器的FPGA实现

Implementation of parallel pipelined FIR filter based on FPGA

数字信号处理常常是计算密集和高性能应用所要求的。FIR滤波器由于具有稳定性和简单性,在数字信号处理中常被采用。随着实时性和低成本要求的提高,对FIR滤波器的要求也越来越高。单一的流水结构和并行FIR结构都不能很好地满足要求。因此,提出一种FPGA实现的并行流水结构的FIR滤波器的实现方案。

Field Programmable Gate Array is used in many implementation of DSP,which is computeintensive and typically need high performance.FIR filter is a stabilized and simple-structured filter,so it is often used in digited signal processing.As the need of real time processing is becoming more and more important,FIR filter using only pipeline technology may not satisfy the needing. On the other hand,the all parallel-structured FIR filter needs much die area.So a new implementation of FIR is given here.