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基于变游程编码的测试数据压缩算法 被引量：32

A Test Set Compression Algorithm Based on Variable-Run-Length Code
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摘要 基于IP核的设计思想推动了SOC设计技术的发展,却使SOC的测试数据成几何级数增长.针对这一问题,本文提出了一种有效的测试数据压缩算法———变游程(Variable-Run-Length)编码算法来减少测试数据量、降低测试成本.该算法编码时同时考虑游程0和游程1两种游程,大大减小了测试数据中长度较短游程的数量,提高了编码效率.理论分析和实验数据表明,变游程编码能取得较同类编码算法更高的压缩效率,能够显著减少测试时间、降低测试功耗和测试成本. SOC technology has developed rapidly, which makes the test data of SOC increasing dramatically. This paper presents an effective test data compression algorithm, Variable-Run-Length code.Both runs of Os and runs of Is in test data stream are mapped to codeword so as to reduce the number of short runs and improve compression radio. Theoretical analysis and experimental results show that Variable-Run-Length code can provide a higher compression radio than other compression algorithms and it also leads to a significant saving in peak and average power due to a careful mapping of the don＇ t-cares in precomputed test sets to 1＇ s and 0＇s,
作者 彭喜元 俞洋
机构地区 哈尔滨工业大学自动化测试与控制系
出处 《电子学报》 EI CAS CSCD 北大核心 2007年第2期197-201,共5页 Acta Electronica Sinica
关键词 变游程编码 测试压缩 测试功耗 variable-run-length code test compression test power dissipation
分类号 TP391.76 [自动化与计算机技术—计算机应用技术]
  • 相关文献

参考文献11

  • 1A Jas, J Chosh-Dastidar. Scan vector compression/de-compression using statistical coding[ A]. IEEE VLSI Test Symposium [ C] .San Diego, California, USA. Apr, 1999.114 - 121.
  • 2T Yamaguchi, M Tilgner, et al. An efficient method for compressing test data [ A ]. the IEEE International Test Conference[ C ]. Washington DC, USA, 1997.79 - 88.
  • 3A Chandra, K Chakrabarty. System-on-a-chip test-data compression and decompression architectures based on golomb codes[ J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2001,20(3) :355 - 368.
  • 4A Chandra, K Chakrabarty. Frequency-directed run length (FDR) codes with application to system-on-a-chip test data compression[ A]. IEEE. VLSI Test Symposium[C].Marina Del Rey, Califomia, USA. 2001.42 - 47.
  • 5P T Gonciari,B M Al-Hashimi. Variable-length input Huffman coding for system-on-a-chip test [ J]. IEEE. Transactions on Computer-Aided Design of Integrated Circuits and Systems,2003,22(6) :783 - 796.
  • 6韩银和,李晓维,徐勇军,李华伟.应用Variable-Tail编码压缩的测试资源划分方法[J].电子学报,2004,32(8):1346-1350. 被引量：26
  • 7A Chandra, K Chakrabarty. A unified approach to reduce SOC test data volume, scan power and testing time [ J]. IEEE Tramactions on Conputer-Aided Design of Integrated Circuits and Systems,2003,22(3) :352- 362.
  • 8J Saxenu,K Butler, L Whetsel. An analysis of power reduction techniques in scan testing[ A ]. IEEE International Test Conference[C]. Baltimore, USA, 2001.670 - 677.
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二级参考文献21

  • 1A Jas,J Ghosh-Dastidar,N A Touba.Scan vector compression/decompression using statistical coding[A].Proceeding of 17th IEEE VLSI Test Symposium[C].Dana Point,California,USA,1999.114-120.
  • 2A Chandra,K Chakrabarty.System-on-a-Chip test data compression and decompression architectures based on Golomb codes[J].IEEE Trans.on CAD of Integrated Circuits and System,2001,20(3):355-368.
  • 3A Chandra,K Chakrabarty.Frequency-directed run length (FDR) codes with application to system-on-a-chip test data compression[A].Proceeding of 20th IEEE VLSI Test Symposium[C].Marina Del Rey,California,USA,2001.42-47.
  • 4A Chandra,K Chakrabarty.Reduction of SOC test data volume,scan power and testing time using alternating run-length codes[A].Proceeding of IEEE/ACM,Design Automation Conference[C].New Orleans,Louisiana,USA,2002.673-678.
  • 5A Chandra,K Chakrabarty.How effective are compression codes for reducing test data volume[A]?Proceeding of VLSI Test Symposium[C].Monterey,California,USA,2002.91-96.
  • 6L Li,K Chakrabarty.Test data compression using dictionaries and fixed-length indices[A].Proceeding of IEEE VLSI Test Symposium[C].Napa Valley,California,USA,2003.219-224.
  • 7Yinhe Han,Yongjun Xu,Xiaowei Li.Co-optimization for test data compression and testing power based On variable-tail code[A].Proceeding of 5th International Conference on ASIC[C].Beijing,P R China,2003.105-108.
  • 8Yinhe Han,Yongjun Xu,Huawei Li,Xiaowei Li,A.Chandra.test resource partitioning based on efficient response compaction for test time and tester channels reduction [A].Proceeding of Asian Test Symposium[C].Xi'an,ShanXi,P R China,2003.440-445.
  • 9K Miyase,S Kajihara,I Pomeranz,M Reddy.Don't-care identification on specific bits of test patterns[A].Proceeding of International Conference on Computer Design[C].Freiburg,im Breisgau,Germany,2002.194-199.
  • 10I Hamzaoglu,J H Patel.Test set compaction algorithms for combinational circuits[A].Proceeding of International Conference on CAD[C].San Jose,California,USA,1998.283-289.

共引文献77

同被引文献281

引证文献32

二级引证文献76

电子学报
2007年 第2期

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