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基于非线性逼近法的QDDFS新构架 被引量：1

A New QDDFS Architecture Base on Non-Linear Approach
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摘要 本文将三角近似法和非线性逼近法相结合,提出了一种高压缩比的设计方案.并对该设计方案进行了详细的理论分析和参数优化,在16 bit的QDDFS系统中,压缩比达到了655.36∶1,并且无失真动态范围(SFDR)优于96dBc,最后给出了本方案的详细结构. Based on the principle of trigonometric approximation and non-liner aooriach,a new QDDFS Architecture with high compression ratio is presented. Its design principle has been analyzed theoretically and all the parameters have also been optimized in Matlab. A high compression ratio of 655.36 is achieved at 96 dBc in a 16bit system.Finally the whole architecture for proposed scheme is given.
作者 赵占锋 周志权 乔晓林
机构地区 哈尔滨工业大学
出处 《电子学报》 EI CAS CSCD 北大核心 2007年第1期1-3,共3页 Acta Electronica Sinica
关键词 DDFS 三角近似法 非线性近似 direct digital frequency synthesizer（DDFS） trigonometric approximation non-linear approach
分类号 TN919.3 [电子电信—通信与信息系统]
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参考文献6

  • 1J Tierney,CMRader,BGold.A digital frequency synthesizer[J].IEEE Trans on Audio and Electro-acoustics,1971,19(1):48-57.
  • 2DA Sunderland,RA Strauch,SSWharfiled,HT-Peterson,CRCole.CMOS/SOS frequency synthesizer LSI circuit for spectrum communications[J].IEEE Journal of Solid State Circuit,1984,19(8):497-505.
  • 3H T NicholasIII,HSamueli,BKim.The optimization of direct digital frequency synthesizer performance in the presence of finite word length effect[A].Baltimore,IEEE Proceedings of the 42nd Annual Frequency Control Symposium[C].Baltimore:IEEE,1988.357-363.
  • 4Shyuan Liao,Liang-Gee Chen.A low-power low voltage direct digital frequency synthesizer[J].VLSI Systems,Technology and Application,1997(6):265-296.
  • 5F Curticapean,KiPalomaki,JNaiittylahti.Direct digital frequency synthesizer with high compression ratio[J].Electronics Letters,2001(11):1275-1276.
  • 6Maoliu Lin,Qinghua Xu,Xiaohui Qi.Quad-rature direct digital frequency sythesizers with super high memory compression ratio and its parameter optimization[A].Wireless/Mobile Communications (8) & Signal Processing for Communication (3),Proceedings of ISCIT2005[C].Beijing:IEEE,2005.1134-1137.

同被引文献7

  • 1J Tiemey, C M Rader, B Gold. A digital frequency synthesizer [ J ]. IEEE. Transactions on Audio Electroacoust, 1971, AU-19 (1) :48 - 57.
  • 2D ASunderland, R A Strauch, S S Wharfiled, H T Peterson, C R Cole. CMOS/SOS frequency synthesizer LSI circuit for spectrum communications[ J].IEEE. J Solid State Circuit, 1984,SC- 19(8) :497 - 505.
  • 3H T Nicholas, Ⅲ, H Samueli, B Kim. The optimization of direct digital frequency synthesizer performance in the presence of finite word length effect [ A ]. In Proc IEEE 42nd Annual Frequency Control Symposium [ C ]. Baltimore: reEF. Press, 1988.357 - 363.
  • 4Shyuan Liao, Liang-Gee Chen. A low power low voltage direct digital frequency synthesizer[A]. Proc Int Symp VLSI Systems [ C]. Technology and Application, 1997.265- 296.
  • 5F Curficapean, K I Palomaki, J Naiittylahti. Direct digital frequency synthesizer with high compression ratio[ J]. Electronics Letters, 2001,37(21) : 1275 - 1276.
  • 6Maoliu Lin, Qinghua Xu, Xiaohui Qi. Quadrature direct digital frequency sythesizers with super high memory compression ratio and its parameter optimization[ A]. Proceedings of IEEE International Symposium on Communications and Information Technology (ISCIT) [ C]. IEEE Press,2005,1134- 1137.
  • 7Usman Hai, Muthammad Nadir Khan, Muthammad Saad Imran, Muhammad Rehan. Compressed ROM high speed direct digital frequency synthesizer architecture[ A ]. The 17th International Conference on Microelectronics (ICM) [ C]. IEEE. Press,2005, 36 - 39,

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电子学报
2007年 第1期

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