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A 155Mbps 0.5μm CMOS Limiting Amplifier

155Mbps速率级0.5μm CMOS限幅放大器(英文)
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摘要 This paper presents a 155Mbps limiting amplifier for STM-1 systems of SDH optical communication. It is implemented in CSMC 0.5μm CMOS technology. Under a supply voltage of 3.3V, it has a power consumption of 198mW. The core of the circuit is composed of 6 cascaded amplifiers that are in a conventional structure of differential pairs,an output buffer, and a DC offset cancellation feedback loop. The small signal gain can be adjusted from 74 to 44dB by an off-chip resistor. The chip was packaged before being tested. The experimental results indicate that the circuit has an input dynamic range of 54dB and provides a single-ended output swing of 950mV. Its output eye diagram remains satisfactory when the pseudo-random bit sequence (PRBS) input speed reaches 400Mbps. 描述了用于SDH光纤通信STM-1速率级光接收机主放大器的155Mbps限幅放大器.该电路采用CSMC0.5μm CMOS工艺实现,供电电压为3.3V,功耗为198mW.核心电路包含6级级联的传统差分放大器,一个输出缓冲和一个直流失调补偿反馈环路.通过调整片外电阻Rset,小信号增益在44~74dB范围内可调.芯片封装后测试得到的输入动态范围为54dB(Rset=50Ω),单端输出摆幅为950mV,在高达400Mbps伪随机码输入时,所得眼图仍然令人满意。
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第2期176-181,共6页 半导体学报(英文版)
关键词 optical communication limiting amplifier CMOS technology SDH 光通信 限幅放大器 CMOS工艺 同步数字序列
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参考文献7

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