基于FPGA的字符串匹配算法

An Implementation of String Matching Based On FPGA

在全字节比较法的基础上提出了一种基于FPGA的子字符串LUT重用算法。该算法通过位宽扩展,以及流水线间字符串、LUT共享,用低端FPGA成功解决了高速字符串匹配问题,与传统字符串匹配算法相比,该算法大幅缩小了匹配算法芯片资源的占用率,是一种高效的并行多模式字符串匹配算法。

In this article, on the basis offuU byte comparator, we put forward a hardware string match algorithm （SubString ＆ LUT Reuse（SSLR）algorithm）based on field programmable gate arrays（FPGA）. By extending the width of databus, and sharing the common sub-logic and look-up Table（LUT） using pipeline in the design, we solve the high-speed string match problem by a general FPGA successfully. Compared to traditional string match algorithms, our algorithm can effectively shrink the chip-area of the string match filter, and it has been proven to be a highly effective parallel multi- string match algorithm.