一种改进的模拟占空比矫正电路

An Improved Analog Duty Cycle Correction Circuit

基于PWLL结构的占空比矫正电路虽然克服了传统占空比矫正电路输出时钟上升沿在占空比矫正过程中发生变化的缺点，但其核心电路——频率电压变换电路不能工作在100MHz以上的频率范围，并且随着工作频率的升高，调整范围会变小。采用pullpush电荷泵代替频率电压变换电路，设计了一个工作在200MHz的占空比矫正电路，HSPICE仿真结果表明其调整范围为30％-70％，占空比变化在1个ps以下，达到了设计要求。

The drawback of the traditional duty cycle correction circuits, the varied input clock rising edge in the duty cycle correction course, has been overcame by duty cycle correction circuit consisted of PWLL architecture overcomes but the core circuit of PWLL - FVC can not work over 100MHz, and the adjustment range becomes small as the working frequency raises. This paper uses pullpush charge bump instead of FVC, and a 200MHz duty cycle correction circuit is designed .The hspice simulation indicates that the adjustment range is 30%-70% and variation of the duty cycle is smaller than lps.So this design reaches the design requirement.