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用于10位100MS/s流水线A/D转换器的采样保持电路 被引量：3

A Sample/Hold Circuit for 10-Bit 100 MS/s Pipelined A/D Converters
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摘要 设计了一个用于10位100 MHz采样频率的流水线A/D转换器的采样保持电路。选取了电容翻转结构;设计了全差分套筒式增益自举放大器,可以在不到5 ns内稳定在最终值的0.01%内;改进了栅压自举开关,减少了与输入信号相关的非线性失真,提高了线性度。采用TSMC 0.25μm CMOS工艺,2.5 V电源电压,对电路进行了仿真和性能验证,并给出仿真结果。所设计的采样保持电路满足100 MHz采样频率10位A/D转换器的性能要求。 A sample-and-hold （S/H） circuit for 10-bit 100 MS/s pipelined A/D converters is presented. The S/ H circuit is based on the capacitor flip-around architecture with gain-boosted telescopic cascode amplifier, which can settle in less than 5 ns at 0. 01% of the final value. A modified bootstrapped switch reducing nonlinearity related to input signal was designed. The circuit is simulated and analyzed based on TSMC＇s 0. 25 μm CMOS process. Simulation results show that the S/H circuit has a good performance that meets the requirement of 10-bit A/D converter with 100 MHz sampling frequency.
作者 陈美娜 戴庆元 朱红卫 姜申飞
机构地区 上海交通大学微纳科学技术研究院
出处 《微电子学》 CAS CSCD 北大核心 2007年第1期89-92,100,共5页 Microelectronics
关键词 采样保持电路 增益自举放大器 栅压自举开关 流水线ADC Sample/hold circuit Gain-booster amplifier Bootstrapped switch Pipelined A/D converter
分类号 TN432 [电子电信—微电子学与固体电子学]
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参考文献6

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同被引文献16

  • 1谭珺,唐长文,闵昊.一种100MHz采样频率C MOS采样/保持电路[J].微电子学,2006,36(1):90-93. 被引量：9
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微电子学
2007年 第1期

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