一种阵列布局优化的256kb SRAM

A 256 kb SRAM with Optimized Array Architecture

介绍了一种阵列布局优化的256 kb(8 k×32位)低功耗SRAM。通过采用分级位线和局部灵敏放大器结构,减少位线上的负载电容;通过电压产生电路,获得写操作所需的参考电压,降低写操作时的位线电压摆动幅度,有效地减少了SRAM读写操作时的动态功耗。与传统结构的SRAM相比,该256 kb SRAM的写功耗可减少37.70 mW。

A 256 kb（8 k×32 b）low power SRAM with optimized array architecture is presented, in which hierarchical bit line and local sense amplifiers are used. The capacitance of bit lines is reduced by using the hierarchical bit line. Voltage generation circuit is used to generate reference voltage, and voltage swing of bit lines is reduced for write operation, so that the power consumption of SRAM for both read and write is reduced effectively. Compared to the conventional SRAM, the 256 kb SRAM can save 37. 70 mW of power for write operation.