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动态时序分析及其在纳米级IC设计中的应用

Dynamic Timing Analysis and Its Application in Nanometer IC Design
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摘要 文章讨论了动态时序分析算法及其在纳米级IC设计中的应用.首先,针对静态敏化算法存在的静态伪路径(StaticFalsePath)问题,提出了动态敏化算法,分析了静态敏化和动态敏化的关系.最后讨论了在电源噪声和串扰噪声影响下的动态时序分析.实验结果表明,串扰噪声条件下的动态时序分析结果比静态时序分析给出的保守结果准确得多. This paper addresses dynamic timing analysis and its application in nanometer technology integrate circuits design. Firstly, dynamic sensitization is presented to deal with static false path in static timing analysis. The corre3ation between static sensitization and dynamic sensitization is discussed. Finally, its application in timing verification considering power noise and crosstalk noise is provided. Experiments show that dynamic timing analysis can present more accurate results than that of static timing analysis.
出处 《电子器件》 CAS 2007年第1期13-16,21,共5页 Chinese Journal of Electron Devices
关键词 动态时序分析 静态敏化 动态敏化 电源噪声 串扰噪声 dynamic timing analysis static sensitization dynamic sensitization power noise crosstalk noise
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参考文献14

  • 1Nagal L W.SPICE2:A Computer Program to Simulate Semiconductor Circuits[R].Memo ERL-M520,Department of Electrical Engineering and Computer Science,University of California,Berkeley,May 1975.
  • 2Benkoski J,et al.Timing Verification Using Statically Sensitizable Paths[J].IEEE Transactions on Computer-Aided Design vol.9,1990:1073-1084.
  • 3Perremans S,Clacsen L,De Man H.Static Timing Analysis of Dynamically Sensitizable Paths[C]//Proceeding of 26th Design Automation Conference,1989:568-573.
  • 4Kirkpatrick T I,Clark N R.PERT as an Aid to Logic Design[J].IBM Journal of Research and Development,vol.10,1966:135-141.
  • 5Roth J P.Diagnosis of Automata Failures:a Calculus and a Method[J].IBM Journal of Research and Develop,July,1966:278-291.
  • 6Devadas S,Keutzer K,Malik S.Computation of Floating Mode Delay in Combinational Circuit:Theory and Algorithms[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems,vol.12,no.12,1993:1913-1923.
  • 7Chang Y S,Gupta S K,Breuer M A.Analysis of Ground Bounce in Deep Sub-Micron Circuits[C]//Proceedings of the 15th IEEE VLSI Test Symposium (VTS97),April,1997:110-116.
  • 8Chen H H,Ling D D.Power Supply Noise Analysis Methodology for Deep Submicron VLSI Chip Design[C]//Proceeding of Design Automation Conference,June,1997:638-443.
  • 9Jiang Y M,Cheng K T,Krstic A.Estimation of Maximum Power and Instantaneous Current Using a Genetic Algorithm[C]//Proceedings of Custom Integrated Circuits Conference,May 1997:135-138.
  • 10Chen P,Kirkpatrick D A,Keutzer K.Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise[C]//Proceeding of the International Conference on Computer Aided Design,San Jose,California,2000:331-337.

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