改进型booth华莱士树的低功耗、高速并行乘法器的设计

Low Power and High-Speed Parallel Multiplier Design Using Modified Booth Wallace Tree

采用一种改进的基-4BOOTH编码和华莱士树的方案,设计了应用于数字音频广播(DAB)SOC中的FFT单元的24×24位符号定点并行乘法器.通过对部分积的符号扩展、(k:2)压缩器、连线方式和最终加法器分割算法的优化设计,可以在18.81ns内完成一次乘法运算.使用FPGA进行验证,并采用chartered0.35μmCOMS工艺进行标准单元实现,工作在50MHz,最大延时为18.81ns,面积为14329.74门,功耗为24.69mW.在相同工艺条件下,将这种乘法器与其它方案进行比较,结果表明这种结构是有效的.

A low power and high-speed 24× 24-b signed fixed point multiplier with modified booth encodes and wallace tree for FFT unit in DAB SOC is presented. An 18. 81-ns multiplication time is achieved at 50 MHz, by optimizing modified signed extension algorithm, （k： 2） compressors, connection algorithm and partition method of final adder. This multiplier has been verified in FPGA and implemented in chartered 0. 35 micron CMO6 standard cell technology, with its frequency being 50 MHz and its area 14 329. 74 gates, power 24. 69 mW. This architecture is compared with some other architectures using the same technology, and the result shows that it is effective and efficient.