摘要
针对浮点ALU中加减运算要求同时计算sum和sum+1的特点,综合考虑延时和面积,采用选择进位结构设计复合加法器。给出了选择进位加法器延迟时间与分组方式的关系,以及最优化分组方法,将其应用于复合加法器的设计中,并用HSPICE在0.18?mCMOS工艺下的模拟结果进行验证。
An optimal design of Carry-select compound adder is presented. The architecture is proposed because sum and sum ＋ 1 must be computed simultaneously in floating-point ALU. The relationshi Pbetween delay time and stage size of CSA is introduced. The optimization is applied to the compound adder design and is proved by HSPICE simulation in 0. 187 m CMOS process.
出处
《微计算机应用》
2007年第3期278-281,共4页
Microcomputer Applications
