2-GHz CMOS锁相环时钟发生器研究与设计

A 2-GHz CMOS phase-locked loop clock generator research and design

采用包含预充电通路,自适应偏置的压控振荡器,设计了一种2-GHz锁相环时钟发生器,并用0.18μm混合信号CMOS工艺实现。分析了环路参数对锁相环输出噪声影响,并对环路参数进行优化。1.8V电源电压下2GHz时钟的rms抖动,peak-peak抖动的测试结果分别为7.27ps,37.5ps,功耗为42mW。

A high speed CMOS PLL clock generator is introduced. A self- biased VCO composed of dual-delay path ring oscillator is designed for low supply voltage, high speed and low jitter. By analysis of relationship between jitter and PLL loop parameters, optimized loop parameters are derived to achieve low output jitter. This design is implemented in 0.18um mixed signal CMOS process, Rms jitter and pk-pk jitter are 7.27ps and 37.5ps @2GHz respectively.