摘要
利用SOPC Builder可以在很短的时间内把NIOS II CPU、Avalon总线、外围设备和存储器接口、片内调试模块等集成在一起生成系统需要的NIOS II处理器,然后用Quartus II设计软件把NIOS II处理器和GPS接口、GSM接口及其它外部设备接口结合在一起编译下载到FPGA芯片中即完成系统的硬件设计;软件设计通常采用C/C++语言编写并用NIOS II IDE编译下载到FPGA中。
It was taken very short time to integrate NIOS Ⅱ CPU, the Avalon address lines, the interfaces of peripherals and memories and the inner debug module into the requisite NIOS H processor using the SOPC Builder. Then it needed to use the Quartus Ⅱ design software to combine N-IOS Ⅱ processor with GPS intefface,-GSM interface and other peripheral interfaces, finishing the hardware design by compiling and downloading it into the FPGA chip. The software was usually writed with C or C++ language and to be compiled and downloaded into FPGA by NIOS HIDE.
出处
《铁路计算机应用》
2007年第2期26-29,共4页
Railway Computer Application