基于FPGA的高速巴切奇偶排序网络的实现

The Realization of High-Speed Batcher's Odd-Even Sort Network Based on FPGA

巴切奇偶排序网络是使用最广泛的硬件排序算法之一,大量运用在网络通信设备中。实现巴切奇偶排序网络需要进行大量复杂的内部布线,采用传统分离元件的设计方法器件尺寸大、可靠性低、速度慢、不易修改升级。文章利用FPGA(可编程门阵列)来实现巴切奇偶网络,解决了传统设计存在的问题,并对巴切奇偶网络的扩展性进行了研究。实验研究验证了设计的正确性。

Batcher＇s Sort Network is one of the most widely used hardware sorting algorithm. It is widely used in network communication devices. The implementation of Batcher＇s Sort Network is very difficult. The design based on the traditional element separating has many problems such as large size, low reliability, low speed, difficult to modify and update. In this paper, these problems are overcome by realizing Batcher＇s Sort Network with FPGA, and the expansibility of Barther Sort Network is explored. We have used timing analysis and simulations to evaluate the design and proved it valid.