现场可编程门阵列动态重构下的低功耗研究

Research on low power consumption of field-programmable gate arrays in run-time reconfiguration

提出了一个开关级模型来估算在不同布线结构参数(输入端口和输出端口的连接块复杂度)下现场可编程门阵列(FPGA)在动态重构(RTR)工作状态下的功耗,并对基于查找表(LUT)和逻辑块结构的FPGA,给出了用于估计电容的FPGA基元等效电路.在功耗估计部分考虑了动态重构下被激活逻辑块的统计分布,使用改进型fpgaEva-LP构架,同时分析电容和开关转换频率,进而估算出功耗,并得出了连接块的复杂度与功耗的关系.结果表明,合理地选择连接块的复杂度可以有效地降低功耗.

To reduce the power consumption of field-programmable gate arrays （FPGA） in run-time reconfiguration （RTR）, a switch-level model was proposed for power efficiency analysis under different architecture parameters such as connection block flexibility consisting of input flexibility and output flexibility. The equivalent circuits of FPGA elements were given to evaluate the load capacitances of the FPGA based on look up table （LUT） cluster-based inland-style. The normal distribution of the activated logic modules was considered in the power evaluation. Using the improved fpgaEva-LP framework, total FPGA power consumptions under different connection block flexibility were obtained by analyzing capacitances and switch frequencies simultaneously. The relationship between connection block flexibility and power consumption was derived. The result shows that reasonable selection of connection block flexibility can effectively lower power consumption.