期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

一种改进的高性能全差分电荷泵设计 被引量：2

Design of an Improved High Performance Differential Charge Pump
下载PDF
导出
摘要 简要讨论了电荷泵中的非线性问题及常用的一些结构,提出了一种改进的基于负反馈的全差分电荷泵结构。它由充电/放电模块,共模反馈电路以及偏置电路组成。负反馈结构使得输入能有效跟踪输出,实现高的上下电流匹配;而共模反馈通过稳定输出静态工作点来抑制差分输出线上的共模扰动。为了测试电荷泵对锁相环路的影响,基于0.25μm 2.5 VCMOS工艺实现了一个电荷泵原型,并用verilogA对锁相环路的其它模块建模。仿真和计算表明:在0.3 V到2.3 V的电压范围内,电流静态失配小于0.01%,在100 kHz环路带宽下,能获得<-75 dBc的杂散电平,适合应用在高性能的锁相环中。 The nonlinearities and some general structures of charge pump are briefly discussed in the paper. An improved differential charge pump based on negative feedback is then presented. It comprises two charge/discharge blocks, a common-mode feedback （CMFB） block and a bias circuit. The negative feedback circuit makes the input effectively track the output, achieving a high up/down current matching regardless of output voltage. The CMFB circuit is utilized to reduce the common-mode disturbance of differential output lines by stabilizing the static operation solution. In order to test charge pump＇s influence in a PLL, a charge pump prototype is implemented using a 0. 25 um 2. 5 V CMOS technology, and the other blocks in PLL loop are modeled based on verilogA language. Simulation and calculation shows that the charge pump has a 〈0. 01% mismatching in 0. 3-2.3 V range, and a 〈-75 dBc spur level in a 100 kHz loop bandwidth, which is suitable for high performance PLL.
作者 黄水龙 王志华
机构地区 清华大学电子工程系
出处 《电子器件》 EI CAS 2006年第4期1053-1057,共5页 Chinese Journal of Electron Devices
基金 国家高技术研究发展计划资助项目(60475018) 国家重点基础研究发展规划的部分支持(G2000036508)
关键词 电荷泵 锁相环 杂散信号 charge pump PLL spur signal
分类号 TN702 [电子电信—电路与系统]
  • 相关文献

参考文献9

  • 1黄水龙,王志华.CMOS分数频率综合器设计技术[J].微电子学,2005,35(4):394-399. 被引量：5
  • 2Best R E.Phase-Locked Loops,Theory,Design and Applications (2nd ed)[M].McGraw-Hill,1993.
  • 3Maneatis J G.Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques[J].IEEE Journal of Solid-State Circuits,Nov.1996,(31):1723-1732.
  • 4Rhee W.Design of High-Performance CMOS Charge Pumps in Phase-Locked Loops[C]//Proc.IEEE International Symposium on Circuits and Systems,Jun.1999,ISCAS'99 (2):545-548.
  • 5Kaenel V,Aebiseher D,Piguet C,and Dijkstra E.A 320 MHz 1.5 mW at 1.35 V CMOS PLL for Microprocessor Clock Generation[C]//Proc.IEEE International Solid-State Circuits Conference,Feb.1996,(39):132-133.
  • 6Young I A,Greason J K,and Wong K L,A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors[J].IEEE Journal of Solid-State Circuits,Nov.1992,(27):1599-1607.
  • 7Johnson M and Hudson E.A Variable Delay Line PLL for CPU-Coprocessor Synchronization[J].IEEE Journal of Solid-State Circuits,Oct.1988,(23):1218-1223.
  • 8Hormoz Djahanshahi,Salama Andre T,Differential CMOS Circuits for 622 MHz/933 MHz Clock and Data Recovery Applications[J].IEEE Journal of Solid-State Circuits,Jun.2000,(35):847-855.
  • 9Kundert K.Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizer[EB/OL].Available From www.Designers-guide.com,May,2003.

二级参考文献38

  • 1Reinhardt V. Spur reduction techniques in direct digital synthesizers [A]. Proc 47th Frequency Control Symp [C]. 1993. 230-241.
  • 2Kundert K S. Introduction to RF simulation and its application[J]. J Sol Sta Circ, 1999, 34 (9): 1298-1319.
  • 3Perrott M H, Trott M D, Sodini C G. A modeling approach for ∑-△ fractional-N frequency synthesizers allowing straightforward noise analysis [J]. IEEE J Sol Sta Circ, 2002, 37 (8): 1028-1038.
  • 4De Muer B, Steyaert M S J. On the analysis of ∑-△ fractional-N frequency synthesizers for high-spectral purity [J]. IEEE Trans Circ and Syst-Ⅱ: Analog and Digital Signal Processing, 2003, 50 (11) : 784-793.
  • 5Brigati S, Francesconi F, Malvasi A, et al. Modeling of fractional-N division frequency synthesizers with Simulink and Matlab [A]. Int Conf Electronics, Circuits and Systems [C]. 2001. 1081-1084.
  • 6Lee K. A single-chip 2. 4 GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique [J].IEEE J Sol Sta Circ, 2001, 36 (5): 800-809.
  • 7Rhee W. Design of low-jitter 1-GHz phase-locked loops for digital clock generation [A]. IEEE Proc ISCAS [C]. 1999. 520-523.
  • 8Nakagawa T, Ohira T. A phase noise reduction technique for MMIC frequency synthesizers that uses a new pulse generator LSI [J]. IEEE Trans Microwave Theory and Technique, 1994, 42 (12) : 2579-2582.
  • 9Riley T A, Copeland M, Kwasniewski T. Delta-sigma modulation in fractional-N frequency synthesis [J].IEEE J Sol Sta Circ, 1993, 28 (5) : 553-559.
  • 10Shu K, Sanchez-Sinencio E, Maloberti F, et al. A comparative study of digital ∑-A modulators for fractional-N synthesis [A]. Int Conf Electronics, Circuits and Systems [C]. 2001. 1391-1394.

共引文献4

同被引文献10

引证文献2

二级引证文献5

电子器件
2006年 第4期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部