VHDL语言在数字电路实验中的应用

Application of VHDL in Digital Circuit Experiment

传统数字电路实验通常采用TTL或CMOS芯片,不能满足现代数字系统设计的要求。而应用VHDL的数字电路实验降低了数字系统的设计难度,因而应用更加广泛。通过介绍VHDL语言及VHDL语言的程序结构和设计流程,以数字钟为例描述VHDL语言设计数字电路模块化、自顶向下的设计方法,从而说明VHDL语言在数字电路实验中的优点,对实验教学有一定的指导作用。

TTL or CMOS chips are generally used in traditional digital circuit experiment, which can not meet the demands of the digital system designing nowadays. Because the digital circuit experiment utilized very - high - speed integrated circuit hardware description language （VHDL） may reduce the difficulties of digital system designing,it is used more widely. A brief introduction of VHDL is given,the program structure and designing flow of VHDL are explained and the digital clock is used as an example to illuminate the designing method of VHDL that is applied to the design of digital circuit - modularization and Top- Down,therefore the advantages of the digital circuit experiment utilized VHDL over the traditional digital circuit experiment are described,which is helpful for experiment teaching to some extent.