Verilog HDL代码描述对状态机综合的研究

Research on Verilog HDL Coding Description for FSM Synthesis

Verilog HDL语言在芯片设计中应用广泛,而有限状态机的设计是数字系统设计的关键部分。本文介绍了有限状态机的设计,探讨了Verilog HDL代码描述会对状态机的综合结果产生的影响,最后通过一个序列检测器的设计进行实例说明。

Verilog HDL is widely used in ASIC design, and FSM is the important part in digital system design. The paper introduces the FSM design. An approach of different coding description of FSM using Verilog HDL and corresponding synthetical circuit are presented. At last, the design of a synthetical sequence - inspected equipment is used as an example.