基于FPGA的FIR升余弦滚降滤波器设计与实现

Design and Implementation of Raised Cosine Roll-off FIR Filter Based on FPGA

为了降低FIR滤波器对FPGA资源的消耗,同时能够直接验证其滤波性能。文中采用乘法器和加法器共享以及MEALY型状态机的实现方法,以及卷积、插零等算法,来实现FIR升余弦滚降滤波设计,同时给出了在Quartus II环境下的时序仿真结果。实践表明,此方法可以节省大量的FPGA资源,仅仅需要100多个LE逻辑单元,就可以有效解决FIR数字滤波器算法在FPGA设计中资源紧张的问题。

In order to reduce FPGA resources consumption and to directly verify the function of FIR filter, multiplier processing instruments, sharing MEALY-state machine method and convolution and interpolation algorithm are adopted to achieve the raised cosine roll-off FIR filter design, The timing simulation results in Quartus Ⅱ environment is also given in this paper. The practice shows that this method can save a lot of FPGA resources, which just need over 100 LE logic unit to effectively solve the FIR digital filter design algorithms in FPGA resource issues.