VHDL高级综合前词法语法分析的研究与实现

Study and Realization of VHDL Lexical Analyzer and Syntax Analyzer before High Level Synthesis

利用YACC与LEX来完成VHDL语言高级综合前端的词法与语法分析器设计。介绍词法分析模块,语法分析模块以及错误处理模块的设计方法。利用Windows平台下的Parser Generator2.0生成词法与语法的C文件,在Visual C++6.0中编译该C文件,生成可执行程序。

A lexical parsing and a syntax parsing for the former design of VHDL programming language compiler are designed by using YACC and LEX. It introduces the design of lexical analyzer model, syntax analyzer model and error process model in details. C type file is generated using Parser Generator 2.0 basing Windows board, and compiled by Visual C++6.0. It introduces the method of lexical analyzer and syntax analyzer by using the Parser Generator 2.0 and Visual C++6.0.