摘要
An asynchronous high-speed pipelined 32×8-bit array multiplier based on latched differential cascode voltage switch with pass-gate （LDCVSPG） logic is presented. The multiplier is based on 4-phase dual-rail protocol. HSPICE analysis using device parameters of Central Semiconductor Manufacturing Corporation （CSMC＇s） 0.6μm CMOS technology is also given, and the result shows that the average data throughput of the multiplier is 375 MHz.
An asynchronous high-speed pipelined 32×8-bit array multiplier based on latched differential cascode voltage switch with pass-gate （LDCVSPG） logic is presented. The multiplier is based on 4-phase dual-rail protocol. HSPICE analysis using device parameters of Central Semiconductor Manufacturing Corporation （CSMC＇s） 0.6μm CMOS technology is also given, and the result shows that the average data throughput of the multiplier is 375 MHz.
基金
Supported by the National High Technology Research and Development Program of China (2001AA141040)
