摘要
LDPC码用迭代概率译码算法能接近香农限,但编码器常具有码长二次方的复杂度。论文介绍了一种基于Q矩阵的准规则LDPC码编码器直接用H矩阵进行设计,简化了H矩阵存储量,采用半并行结构,能进行运算量为线性复杂度的快速编码。编码器在Xilinx Virtex2 XC2V1000上用Verilog语言完成了物理实现。
LDPC Codes is a kind of linear group codes which can be near the Shannon limit, but the complexity of directly encoding LDPC Codes is the square of the length of codeword. In this article, we introduce how to construct LDPC codes with linearly encoding complexity used by Q-Matrix, Then we use semi-parallel architecture to simplify complexity of multipliers, reduce the required memory for storing ￡＂and we have completed physical implementation on Xilinx Virtex2 XC2V 1000 in Verilog language by Xilinx ISE software,
出处
《信息安全与通信保密》
2007年第4期54-55,59,共3页
Information Security and Communications Privacy
关键词
LDPC码
Q矩阵
半并行结构
LDPC Code
Q-Matrix
semi-parallel architecture
