一种新型删信删余RS码译码器

Novel shortened-and-punctured reed-solomon decoder

针对传统Reed-Solomon(RS)码译码器不适合IEEE802.16d系统的RS码的译码问题,提出了一种新的可变速率删信删余RS码译码器优化设计结构.在编码器中,采用系数对称的生成多项式,减少了迦罗华域(GF)乘法器的个数.在译码器中,采用改变修正的欧几里德算法(MEA)中的初始条件来求解关键方程,并在传统删信RS码译码器的基础上,设计了新的删信删余RS码译码器结构.在现场可编程门阵列((FPGA)芯片上实现和验证了该设计结构,同时针对IEEE802.16d系统中六种不同码型的RS码,分析了在给定工作时钟的条件下可以达到的最大译码吞吐率.结果表明,该译码器结构可以达到至少30Mbps的译码吞吐率,能够满足IEEE802.16d系统的要求.

To resolve the incapability of decoding Reed-Solomon （RS） codes of conventional RS decoders in IEEE802.16d system, optimized design architecture for rate-variable shortened-and-punctured RS decoder was presented. A symmetric generator polynomial was applied, and the number of Galois-field （GF） multiplications was reduced in the encoder. In the decoder, the key function was solved by altering the initial condition of the modified Euclid algorithm （MEA）, and a novel shortened-and-punctured RS decoder archi- tecture was proposed based on conventional punctured RS decoder. The design architecture was implemented and verified in field program gates array （FGPA） chips, and the maximum decoding throughput of six types of RS codes in IEEE802.16d system was analyzed at a particular working clock respectively. The results show that the proposed decoder architecture can achieve a decoding throughput of at least 30 Mbps, and satisfy the requirement of IEEE802.16d system.